The moment of truth: virtues and limitations of commodity Hardware Transactional Memory

The multi-core revolution that took place nearly one decade ago has turned parallel programming into a major concern for mainstream software development industry. In this context, Transactional Memory (TM) has emerged as a simpler, attractive alternative to lock-based synchronization, whose complexity and error-proneness are widely recognized. On the other hand, performance of TM has been a matter of controversial debate, as existing software implementations (STMs) need to incur in instrumentation overheads that can hinder their efficiency compared to fine-grained locking schemes. Recently, this landscape has been profoundly changed by the integration of Hardware TM (HTM) in the last generation of Intel processors, which raised a number of questions on the future of TM, such as: will the availability of HTM support turn TM into a mainstream paradigm? What role will STM play now that HTM is available in commodity architectures? We seek answers to these questions by conducting the largest study on TM to date, comparing different locking techniques, hardware and software TMs, as well as different combinations of these mechanisms, from the dual perspective of performance and power consumption. Our study sheds a mix of light and shadows: on one hand, we identify workloads in which HTM clearly outperforms existing synchronization mechanism; on the other hand, current HTM implementations suffer of severe restrictions, which limit significantly the scope in which these can be more effective that state of the art STM solutions. We also highlight the urge for designing more effective approaches for using HTM and STM in synergy, as existing hybrid solutions suffer from excessive overheads that nullify their potential benefits.